On the 6502 Microprocessor

by John Carlsen, 13DEC2023

I was born and raised in Silicon Valley.

Shortly after my family moved in 1978 to Sunnyvale—roughly half-way between Apple and Atari—I became fascinated by the microcomputer revolution that started in 1977 with the introduction of the Atari Video Computer System (VCS, later known as the Atari 2600) and Byte Magazine’s “1977 Trinity” of home computers: Apple II, Commodore PET 2001, and Tandy/Radio Shack TRS-80.

Most of these were made possible by the 6502 (“sixty-five oh two”) microprocessor that MOS Technology created in 1975.

The 6502 was the CPU (central processing unit) in both the Apple II and the Commodore PET 2001. One of its variants, 6507, was the CPU in the Atari Video Computer System that popularized cartridge-based video games, which were introduced in 1976 by the Fairchild Channel F Video Entertainment System (VES). (A Fairchild F8 microprocessor was its CPU. The TRS-80’s CPU was a Zilog Z80, which I pronounce “zee eighty” and was released in 1976.)

The popular designs of 6502 and its variants were licensed for manufacture by others including Rockwell International and Synertek.

In 1979, the Atari 400 and Atari 800 computers were introduced using a revised 6502, the 6502B made by Synertek (Atari part number C014377-03). Later units and their successors used a custom 6502 variant that Atari named Sally (Atari part number C014806), which appears to be the basis for the 6502C. (Note that the “C” suffix indicates the third revision—and fourth version—of the mainstream 6502, not the 65C02, which was a CMOS version.)

Some of my neighbors got Atari computers, and one of the key developers of Atari BASIC and Atari DOS had grown up across the street.

After using a borrowed single-board computer (with an RCA 1802 microprocessor) to learn a bit about machine code (hexadecimal representations of instructions and data), I got an Atari 800, became active in the local community of Atari users (largely through the Bay Area Atari Users Group, BAAUG), set up shop repairing Atari products, worked at Atari providing customer technical support (a summer job between my last two years of high school), and about 1.5 years later started working for Atari’s founder, Nolan Bushnell.

Not long afterward, while in college I tested games for Activision and Infocom labels (for Mediagenic) on PCs and the 1985 Nintendo Entertainment System, which used variants of the 6502 made by Ricoh.

Later, while working for video game developer Iguana Entertainment—and moving with it to Austin, Texas—I created interface hardware to enable software-development, including versions for its 1990 successor, the Super Nintendo Entertainment System (SNES), which for its CPU used a modernized derivative of the 6502 based on the Western Design Center (WDC) 65C816 (“sixty-five-see-eight-sixteen”) released in 1983. (The 65C816 was also the CPU in the Apple IIgs released in 1986, which I saw in use at Mediagenic for early development of SNES games.)

Roots in the Motorola 6800

Based in Valley Forge, Pennsylvania, MOS Technology was formed in 1969 by three former executives of General Instrument.

After Motorola released its 6800 (“sixty-eight hundred”) microprocessor in 1974, several of its former designers wished not to be relocated by Motorola from Mesa, Arizona to Austin, Texas. So, they instead joined MOS Technology and in 1975 they created both the 6502 and its sibling the 6501 as simpler, lower-cost, and higher-performance alternatives to the 6800. Though neither the 6501 nor 6502 were compatible with 6800 software, the 6501 could be used as a pin-compatible replacement for the 6800. Both the 6501 and the 6502 were designed to be compatible with support chips for the 6800; for example, the 1976 Apple Computer 1 included both a 6502 CPU and a 6820 PIA (peripheral interface adapter).

In September 1975, the 6501 and the 6502 cost only $20 and $25 (respectively), prompting Motorola in October 1975 to reduce the price of its 6800 from $175 to $69.

In November 1975, Motorola sued MOS Technology, seeking injunction to stop MOS Technology from making and selling microprocessors, claiming patent infringement and misappropriation of trade secrets through seven of its former employees who joined MOS Technology. The pin-compatible 6501 did not survive. (I recall that, when I was a kid becoming interested in computers circa 1980, one of my favorite stores carried adapter modules that would allow a 6502 to be plugged into a circuit board designed for a 6800 microprocessors, allowing a 6502 to nearly mimic the functions of a 6501.)

MOS Technology was acquired in November 1976 by Commodore International (parent of Commodore Business Machines, which later made the PET, VIC-20, Commodore 64, and others), with the condition that the 6502 designer Chuck Peddle would become Commodore’s chief engineer. (I was lucky enough to meet Chuck Peddle briefly in 2016.)

6800’s Legacy

In 1979, Motorola launched its 68000 microprocessor, which dominated much of the second generation of microcomputers as the CPU in Apple Macintosh (1984), Atari ST and Commodore Amiga (both 1985), and the Sega Genesis video game console (circa 1989). It could have been in the IBM PC (1982), though the popular story was that the 68000 wasn’t ready in time to meet IBM’s development timeline. (In 1988, my manager at IBM claimed it had been a marketing decision to use the less-powerful Intel 8088 so that the IBM PC would not be able to compete against its line of workstations.)

Around 1984, Motorola had released microcontrollers based on the 6800, including the popular 68HC11 (“HC” for “high-speed CMOS”) that I had began experimenting with around 1989 after buying a development kit it sold me for $68.11.

After Motorola spun off part of its Semiconductor Products Division in 2004 to create Austin-based Freescale Semiconductor, in or around 2007 I had interviewed to become the program manager for its ColdFire product line, which Motorola had launched in 1994 to offer embedded microcontroller versions of the 68000 series microprocessors it launched in 1979, extending the 6800 microprocessor line. (Though I wasn’t successful in landing the job, I still feel honored to have been interviewed as a candidate.)

How Processors Became Microprocessors

Microprocessors are a type of integrated circuit, which is a type of semiconductor device that integrates many components of a larger electronic circuit into a single device.

Integrated Circuits and Silicon Chips

Integrated circuits are fabricated on flat round wafers sliced from an ingot and then fabricated through processes that combine printing (as through electron-beam lithography from reticles for each process layer), doping, and growing non-conductive oxides. When wafer fabrication is complete, the wafer is scored in two directions along the boundaries of each rectangular (sometimes square) die. While still on the wafer, each die is tested; the bad ones are marked for exclusion and the good ones are removed as “chips” from the wafer and usually packaged with a leadframe so that it may be mounted more easily on a printed circuit board (PCB). Some applications (such as early digital wristwatches) use a process known as chip on board (COB) to mount chips directly to printed circuit boards, where they are wire bonded and encapsulated.

Though germanium or other semiconducting elements may be used, many chips were made from silicon and are therefore called silicon chips. Many early silicon chips were made in California’s Santa Clara Valley, leading to its now-popular metonym Silicon Valley.

The Blocks from which a Computer is Built

The first commercially-available transistorized computers (second-generation computers) became available in the late 1950s. Many computer companies then built transistor-based interchangeable modules to perform basic logic functions on printed circuit board assemblies.

My father worked for one of these companies, Control Data Corporation, and I started learning about electronics and computers with some of the transistor-based assemblies it discarded.

The first computer based on silicon integrated circuits was the Apollo Guidance Computer (AGC), which was introduced in 1966 and enabled people to visit the Moon beginning in 1969.

Small-Scale Integration

The logic chips in the Apollo Guidance Computer are an example of small-scale integration (SSI), through which small numbers of multiple transistors on single chips integrate a function of a larger of a circuit.

The designers of the Apollo Guidance Computer’s original architecture (Block I) were able to simplify their task of qualifying components for spaceflight by building it using only one type of device, which contained two isolated (dual) triple-input NOR gates. This was possible because NOR gates (and NAND gates) are universal logic gates from which any other gate can be made. (Some other types of integrated circuits were added to the later Block II design.)

(These NOR devices were fabricated by Fairchild Semiconductor, at what I believe was either of its Silicon Valley facilities—in north Mountain View or on Bernal Road in south San Jose—which were both later among many Environmental Protection Agency toxic waste Superfund sites in Silicon Valley directly attributable to the early semiconductor industry that gave it its name.)

(In 2019, as part of a celebration of the 50th anniversary of the first people landing on the Moon, for some friends I designed a printed circuit board that connected to and helped some friends restore an Apollo Guidance Computer to operation. Shortly afterward, I happened to meet Margaret Hamilton, who directed software engineering for the Apollo Program and for her work received the Presidential Medal of Freedom from Barack Obama in 2016.)

Types of Transistor Logic

These devices used a resistor-transistor logic (RTL) configuration, through which resistors are used to bias nodes of a circuit toward a binary logic state’s voltage level when not actively driven by a transistor toward the voltage level representing the other binary state.

Texas Instruments had introduced a series of SSI integrated circuits with transistor-transistor logic (TTL) by 1973, when it released its (uniquely hardcover) TTL Data Book for Design Engineers.

As I entered my teenage years, my friend (and formerly my father’s office mate while at the Sunnyvale office of Control Data Corporation) LaFarr Stuart “loaned” me a copy of this book (which I still have and treasure) along with a logic trainer kit made by Digital Equipment Corporation (DEC) and likely intended for college students. My junior high school had once been a high school, so I was able to borrow from its library a copy of Don Lancaster’s 1974 The TTL Cookbook.

One key benefit of TTL is that it doesn’t need as much power to operate as RTL (and DTL, which is diode-transistor logic). This is because the addition of a second transistor effectively shuts off power to the output when the other transistor drives it.

The term TTL describes the configuration of the devices to create the logic circuit, not their construction. Although the first TTL devices used bipolar junction transistors (BJTs), TTL also includes later devices made using field-effect transistors (FETs) including those made using metal-oxide-silicon (MOS) processes, sometimes called MOSFETs.

A key benefit of MOSFETs is that they switch based on voltage levels, not varying flows of current as in BJTs. So, MOSFET circuits are more power efficient than similar circuits constructed from BJTs.

Using MOSFETs, a TTL configuration requires types of both negative-channel MOS (NMOS) and positive-channel MOS (PMOS), a combination called complimentary metal-oxide-silicon (CMOS).

Note that the 6502, 6502A, 6502B, and 6502C were NMOS devices. The WDC 65C02 was a later CMOS device. (The 6502 was released in 1975 and 6502B was used in early Atari 8-bit computers starting in 1979. The 65C02 was released in 1983.)

6502 Architecture

The 6502 design follows the Von Neumann (Princeton) architecture pattern (established in 1945), which essentially doesn’t differentiate addresses for instructions and data as it would had it employed Harvard architecture.

While operating, a 6502 follows a program (ordered list) of instructions to copy data between its registers (X index, Y index, an accumulator, stack pointer, and processor status register) and locations it can address containing random-access memories (including read-only memory, or ROM) or other devices. With this data, it performs simple arithmetic operations and determines which paths of its program to execute.

Processor Status Register Flags

The 6502’s processor status register uses 7 bits as flags to detect and enable certain conditions. These flags are arranged in the order { N V - B D I Z C }, further described in the following table.

Instruction Set

To perform its operations, the 6502 uses a set of 56 instructions. (The first version of the 6502 had only 55 instructions, with the ROR instruction added to later versions.)

Operation Codes

Microprocessors use a number to represent each combintation of intruction and the format it can use for each operation, which are often variations in addressing mode modes available to use the instruction. These numbers are called operation codes, a term often shortened to “op codes” or “opcodes”.

The 6502 (and any other microprocessor that stores opcodes as single 8-bit bytes) can have up to 256 (2⁸) of them. For its 56 instructions and their variants, the 6502 uses only 151 of the 256 possible opcodes. In contrast, the more-expensive Motorola 6800 from which the 6502 was allegedly derived included 197 opcodes to represent 72 instructions and their variations. (If a microprocessor of this era would encounter and attempt to execute an undocumented opcode, its behavior would be likely undesirable and potentially unpredictable.)

Opcode Maps

The instructions and their variations have often been presented in tables often called “opcode maps”. These generally present terse information about each opcode (a mnemonic abbreviation and little else) in square tables of 16 columns by 16 rows, arranged in numerical order based on each opcode number’s lowest 4 bits (corresponding to the least-significant of its two hexadecimal digits) along one axis and the highest 4 bits (the most-significant digit, or MSD) along the other. (Groups of consecutive 4 bits are sometimes referred to as a nibble or nybble, apparently depending on whether one sees it as 4 bits or half a byte.)

Key to colors used to represent addressing modes in the table that follows:

Note that dark gray areas indicate operation codes that are undefined for the 6502.

The thick black borders indicate that the JSR and indirect JMP instructions deviate somewhat from the pattern.

The Trouble with Opcode Maps

For most users, I believe that tables of opcodes arranged by their machine code numbers is about as useful as a table that presents information about the known chemical elements arranged by their colors. Generally, these tables help only if you have only an opcode number and need its mnemonic abbreviation; they make it difficult to infer logical connections between opcodes of similar functions and addressing modes (though some can often be done through color coding).

So, some re-arrangement is in order.

A Better Order for Instruction Bits

Like other microprocessors, especially those of early economical design, the 6502 encodes into a single word (in this case, an 8-bit byte) both the function of the instruction and variations in addressing modes.

Unfortunately for users of square opcode maps, some of the bits used to form one number aren’t adjacent; in the 6502, the 8 bits of an opcode (with the most-significant bit first, on the left) follow the pattern AAABBBCC, where BBB represents the addressing mode. The remaining bits specify the function to be performed. (I expect that there were economic benefits behind such choices when the 6502 was being designed.)

These last bits, I will describe as the code (or number) that defines the instruction.

Rather than keep the groups of bits in their original order to form the pattern AAACC, I find that maps of 6502 opcodes are easier to understand in the order CCAAA. Thus, I present them using that order to form the following table. For simplicity, I keep the bits within those groups in the same order.

For example, the instruction with mnemonic code NOP is represented numerically as hexadecimal 0xEA or binary 11101010. Divided into groups using the pattern AAABBBCC, this is 111 010 10. Swapping the order of groups AAA and CC yields the instruction code 10 111 (23) with the address mode remaining in group BBB as 010 (2), which in the following table correlate to the headings for rows and columns, respectively.

In the table that follows, instructions are organized into groups as below, some with backgrounds color-coded to indicate types of instructions (rather than their addressing mode), as listed below. Additionally, superscript annotations indicate that one or two cycle(s) more (than the minimum number of a given range) will be required when (B) a conditional branch is taken and/or (P) crossing a page boundary.

As in the previous table, addressing modes are highlighted using the same colors and the thick black borders indicate that the JSR and indirect JMP instructions deviate somewhat from the pattern.

What Can Opcode Timing Reveal About the 6502?

You might have noticed that most of the instructions require at least one cycle more than the number of bytes loaded for the opcode and any parameters. For example, a NOP or any register or status instruction requires 1 byte and 2 cycles. (A notable exception is JMP absolute.)

Where to Load the Next Byte?

The next byte fetched via the data bus could be stored in the single-byte register for instruction, X, Y, or stack pointer, or the low or high byte of the accumulator, the high byte of the accumulator, program counter, or an indirection register.