The 6502 Microprocessor

by John Carlsen – February 29, 2024

Recently—in 2024—while seeking information for another project, I noticed that the information available online about the 6502 was incomplete and/or poorly presented, even from some of the best sources, such as 6502.org. So, I made a web-friendly—all HTML—version of Synertek’s printing of the MOS Technology 6500 Family Programming Manual, which I expand upon herein.

The microcomputer revolution started in 1977 with the introduction of the Atari Video Computer System (VCS)—later known as the Atari 2600—and Byte Magazine’s “1977 Trinity” of home computers: Apple II, Commodore PET 2001, and Tandy/Radio Shack TRS-80.

September 1975 advertisement for MOS Technology 6501 and 6502
(click for full image)

Most of these machines—and many that followed—were made possible by the 6502 (“sixty-five oh two”) family of microprocessors created by MOS Technology in 1975 and manufactured by it and by others (“second sources”) including Rockwell International and Synertek. (That year MOS Technology was acquired by Commodore, securing a supply chain for its desktop calculators.)

The 6502 was the CPU in both the Apple II and the Commodore PET (and later Commodore’s 1980 VIC-20 and 1982 CBM-II).

Variants of the 6502 were used in machines including the Atari 2600 VCS, which used a 6507 as its CPU and popularized cartridge-based video games. (These were introduced the previous year, in 1976, by the Fairchild Channel F Video Entertainment System, or VES, which used a Fairchild F8 microprocessor as its CPU.)

Released in 1979, Atari’s line of 8-bit home computers (starting with models 400 and 800) entered production using a revised 6502, the 6502B made by Synertek (Atari part number C014377-03), while later units and their following models used a custom 6502 variant that Atari named Sally (Atari part number C014806), which appears to be the basis for the 6502C. (Note that the “C” suffix indicates the third revision—and fourth version—of the mainstream 6502, not the 65C02, which was a CMOS version.)

While in college I tested games for Mediagenic—the company merged from Activision, Infocom, and others—for PCs and the 1985 Nintendo Entertainment System, which used variants of the 6502 made by Ricoh.

Later, while working for video game developer Iguana Entertainment—and moving with it to Austin, Texas—I created interface hardware to enable software-development, including versions for its 1990 successor, the Super Nintendo Entertainment System (SNES), which for its CPU used a modernized derivative of the 6502 based on the Western Design Center (WDC) 65C816 (“sixty-five-see-eight-sixteen”) released in 1983. (The 65C816 was also the CPU in the Apple IIgs released in 1986, which I saw in use at Mediagenic for early development of SNES games.)

Roots in the Motorola 6800

The 6502 and its many varieties were economical alternatives to the Motorola 6800, and created by many of the designers of the 6800; a short-lived twin of the 6502, the 6501 was pin-compatible with the 6800 (though not software-compatible) until its sales were ended by legal action from Motorola.

Based in Valley Forge, Pennsylvania, MOS Technology was formed in 1969 by three former executives of General Instrument.

After Motorola released its 6800 (“sixty-eight hundred”) microprocessor in 1974, several of its former designers wished not to be relocated by Motorola from Mesa, Arizona to Austin, Texas. So, they instead joined MOS Technology and in 1975 they created both the 6502 and its sibling the 6501 as simpler, lower-cost, and higher-performance alternatives to the 6800. Though neither the 6501 nor 6502 were compatible with 6800 software, the 6501 could be used as a pin-compatible replacement for the 6800. Both the 6501 and the 6502 were designed to be compatible with support chips for the 6800; for example, the 1976 Apple Computer 1 included both a 6502 CPU and a 6820 PIA (peripheral interface adapter).

In September 1975, the 6501 and the 6502 cost only $20 and $25 (respectively), prompting Motorola in October 1975 to reduce the price of its 6800 from $175 to $69.

Chuck Peddle (wearing hat), Ron Nicholson (behind Peddle), and me (John Carlsen, at left) in Santa Clara, CA on September 8, 2016

In November 1975, Motorola sued MOS Technology, seeking injunction to stop MOS Technology from making and selling microprocessors, claiming patent infringement and misappropriation of trade secrets through seven of its former employees who joined MOS Technology. The pin-compatible 6501 did not survive. (I recall that, when I was a kid becoming interested in computers circa 1980, one of my favorite stores carried adapter modules that would allow a 6502 to be plugged into a circuit board designed for a 6800 microprocessors, allowing a 6502 to nearly mimic the functions of a 6501.)

MOS Technology was acquired in November 1976 by Commodore International (parent of Commodore Business Machines, which later made the PET, VIC-20, Commodore 64, and others), with the condition that the 6502 designer Chuck Peddle would become Commodore’s chief engineer. (I was lucky enough to meet Chuck Peddle briefly in 2016.)

Architecture

The 6502 design follows the Von Neumann (Princeton) architecture pattern (established in 1945), which essentially doesn’t differentiate between addresses used for instructions and those used for data, as is done by those that follow Harvard architecture.

While operating, a microprocessor such as the 6502 follows a program, which is just an ordered list of instructions and operands.

It copies data between externally-addressable locations and its registers. A 6502’s registers include an accumulator, X index, Y index, program counter (high byte and low byte), stack pointer (high byte and low byte), and processor status (a collection of bit flags).

The external locations generally include random-access memories (usually including read-only memory, or ROM) and devices that provide interfaces for performing useful functions through sensing and controlling various signals.

With this data, the microprocessor determines which outputs to provide when it receives certain inputs. These often affect which paths of the program are executed and which arithmetic operations are performed in the process.

Processor Status Register

The 6502’s processor status register uses 7 bits as flags to detect and enable certain conditions. These flags are arranged in the order { N V E B D I Z C }, further described in the following table.

The individual flags or bits are often presented in a form as the following figure.

The meanings and functions of the bits are as follows.

Carry Flag (C)

The carry bit which is modified as a result of specific arithmetic operations or by a set or clear carry command has been discussed previously.

In the case of shift and rotate instruction, the carry bit is used as a ninth bit as it is in the arithmetic operation.

The carry flag can be set (to 1) or cleared (to 0) by the programmer. A SEC instruction will set and a CLC instruction will clear the carry flag.

Operations which affect the carry are ADC, ASL, CLC, CMP, CPX, CPY, LSR, PLP, ROL, RTI, SBC, SEC.

Zero Flag (Z)

This flag is automatically set by the microprocessor during any data movement or calculation operation when the 8 bits of results of the operation are 0. Therefore, the bit is on (“1”) when the results are 0, and off (“0”) when the results are not equal to 0.

The feature of the machine is similar to that of the PDP-11 in the sense that operations which are decrementing index registers or memory locations have a built-in test for 0 as a result of decrementing to the 0 condition.

It is also possible to test for 0 condition immediately following load and other logical operations, as opposed to processors which have to do a test and branch instruction.

The Z flag is not directly settable or resettable by an instruction but is affected by the following instructions: ADC, AND, ASL, BIT, CMP, CPY, CPX, DEC, DEX, DEY, EOR, INC, INX, INY, LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, RTI, SBC, TAX, TAY, TXA, and TYA.

Interrupt Disable (I)

The interrupt disable is a flip-flop made use of by the programmer and by the microprocessor to control the operations of the interrupt request pin.

A more detailed discussion of the effects of the interrupt disable are given in the discussion under interrupt control.

However, the purpose of the interrupt disable is to disable the effects of the interrupt request pin. The interrupt disable, I, is set by the microprocessor during reset and interrupt commands.

The I bit is reset by the CLI instruction or the PLP instruction, or at a return from interrupt in which the interrupt disable was reset prior to the interrupt. The interrupt flag may be set by the programmer using a SEI instruction and is cleared by the programmer by using a CLI instruction.

Instructions which affect the interrupt disable are BRK, CLI, PLP, RTI, and SEI.

Decimal Mode Flag (D)

As discussed, the use of the decimal mode flag is to control whether or not the adder operates as a straight binary adder for add and subtract instructions or as a decimal adder for add and subtract instructions.

The SED instruction sets the flag and the CLD instruction resets it.

The only instructions which affect the decimal mode flag are CLD, PLP, RTI, and SED.

Break Command (B)

The break command flag is set only by the microprocessor and is used to determine during an interrupt service sequence whether or not the interrupt was caused by BRK command or by a real interrupt.

A more detailed discussion of BRK is in the interrupt section.

This bit should be considered to have meaning only during an analysis of a normal interrupt sequence.

There are no instructions which can set or which reset this bit.

Expansion Bit (E)

The next bit in the flag register is an unused bit.

It is most likely that this bit will appear to be on when one is analyzing the bit pattern in the processor status register; however, no guarantee as to its state is made as this bit will be used in expanded versions of the microprocessor.

Overflow (V)

As discussed in the section on arithmetic operations, if one is to look at the binary arithmetic operations as signed binary operations, there needs to be some indication of the fact the result of the arithmetic operation has a greater value than could be contained in the 7 bits of the result. This bit is the overflow bit and during ADC and SEC instructions represents a status of an overflow into the sign position. The user who is not using signed arithmetic can totally ignore this flag during his their programming; however, this flag has the same meaning as the carry to the user who is using signed binary numbers. It indicates that a sign correction routine must be used if this bit is'on after an add or subtract using signed numbers.

In addition to its use to monitor the validity of the sign bit in ADC and SBC instructions, the overflow flag in the MCS650X products is dramatically changed from PDP-11 and the MC6800. In those systems the overflow flag was very carefully controlled so as to allow certain signed branches for analysis of signed numbers. These branches have been deleted from the MCS6500 series because of confusion and difficulty often associated with using them, and so therefore, the overflow flag is applicable only to the operation of ADC and SBC, and then only when using signed numbers.

However, in order to maximize the effectiveness of this testable flag the BIT instruction which may be used to sample interface devices, allows the overflow flag to reflect the condition of bit 6 in the sampled field.

During a BIT instruction the overflow flag is set equal to the content of the bit 6 on the data tested with BIT instruction. When used in this mode, the overflow has nothing to do with signed arithmetic but is just another sense bit for the microprocessor.

Instructions which affect the V flag are ADC, BIT, CLV, PLP, RTI, and SBC.

On certain versions of the microprocessor the V bit will also be available for stimulus from the outside world.

Negative Flag (N)

As already discussed, one of the uses of the microprocessor is to perform arithmetic operations on signed numbers. To allow the user to readily sample the status of the sign bit (bit 7), the N flag is set equal to bit 7 of the resulting value in all data movement and data arithmetic. This means, for instance, after a signed add one can determine the sign of the result by sampling the N flag directly rather than finding a way to isolate bit 7. Although signs were the primary purpose for which the N flag was intended, its usefulness far exceeds that of strictly a sign bit.

Because of every operation including simple moves and add operations the N bit is equal to the status of bit 7 as a result of the operation; its primary use becomes that of an easily testable bit. AlmOSt all single-bit instructions, all interrupts and all I/O status flags use bit 7 as a sense bit.

This allows the user to perform some type of memory access operation such as Load A followed by immediate conditional branch based on the status of bit 7 as reflected in the N flag. Like the Z bit, this flag is not settable or controllable by the programmer and represents the status of the last data movement operation.

Instructions which affect the negative flag are ADC, AND, ASL, BIT, CMP, CPY, CPX, DEC, DEX, DEY, EOR, INC, INX, INY, LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, SBC, TAX, TAY, TSX, TXA, and TYA.

Flag Summary

To summarize, the microprocessor treats a series of flags or status bits as a single register called the “P” or “Program Status” register.

Some of these flags are controllable only by the programmer (such as the D flag); others are controllable by both the user program and microprocessor (such as the interrupt disable flag). Some of them are set and reset by almost every processor operation, such as the N and Z flags. Each of these flags has its own meaning to the programmer at a particular point in time.

When combined with the concept of conditional branches, they represent a powerful test and jump capability not normally found in a machine of this magnitude. Other than perhaps the carry flag which is used as part of the arithmetic instructions, the flags by themselves have relatively little meaning unless one has the ability to test them. For this purpose there is a series of conditional branch instructions designed into the machine.

Instruction Set

To perform its operations, the 6502 uses a set of 56 instructions. (The first version of the 6502 had only 55 instructions, with the ROR instruction added after June 1976.)

Each instruction is given a mnemonic abbreviation. To help distinguish them from operands, labels, and other parts of the program code, the 6502 designers uniformly use three letters to abbreviate each instruction, as listed in the following table.

Instruction Groups

The 65XX microprocessor instruction set is divided into three basic groups:

1. Group One has the greatest addressing flexibility and consists of the most general purpose instructions such as Load, Add, Store, etc.
2. Group Two includes the Read, Modify, Write instructions such as Shift, Increment, Decrement and the Register X movement instructions.
3. Group Three contains all the remaining instructions, including all stack operations, the register Y, compares for X and Y and instructions which do not fit naturally into Group One or Group Two.

There are eight Group One instructions, eight Group Two instructions, and all of the 39 remaining instructions are Group Three instructions.

The three groups are obtained by organizing the OPCODE pattern to give maximum addressing flexibility (l6 addressing combinations) to Group One, to give eight combinations to Group Two instructions and the Group Three instructions are basically individually decoded.

Group One Instructions

These instructions are: Add With Carry (ADC), (AND), Compare (CMP), Exclusive Or (EOR), Load A (LDA), Or (ORA), Subtract With Carry (SBC), and Store A (STA). Each of these instructions has a potential for 16 addressing modes. However, in the MCS6501 through MCS6505, only eight of the available modes have been used.

Addressing modes for Group One are: Immediate, Zero Page, Zero Page Indexed by X, Absolute, Absolute Indexed by X, Absolute Indexed by Y, Indexed Indirect, Indirect Indexed. The unused eight addressing modes are to be used in future versions of the MCS650X product family to allow addressing of additional on-chip registers, of on-chip I/O ports, and to allow two byte word processing.

Group Two Instructions

Group Two instructions are primarily Read, Modify, Write instructions.

The primary function of Group Two instructions is to perform some memory operation using the appropriate index.

Each Group One instruction may use all addressing modes (except Immediate mode is not used by STA), which ; in addition to these, Group Two instructions add an addressing mode for the accumulator and other special decodes in this basic group.

There are two subcatagories within the Group Two instructions.

The first subcategory includes the shift and rotate instructions Logical Shift Right (LSR), Arithmetic Shift Left (ASL), Rotate Left (ROL), and Rotate Right (ROR). The four shift instructions all have register A operations.

The second subcategory includes the Increment (INC) and Decrement (DEC) instructions and the additional index register X instructions Load X (LDX), Store X (STX), Load X from A (assigned its own mnemonic, TAX), TXS, TSX, and the special function of Decrement X (DEX), which is one of the special cases of Store X (STX). (The location of NOP suggests it should be included in this subcategory.)

These instructions would normally have eight addressing modes available to them because of the bit pattern. However, to allow for upward expansion, these instructions have only the following addressing modes defined: Zero Page, Zero Page Indexed by X, Absolute, Absolute Indexed by X, and a special Accumulator (or Register) mode. The incremented or decremented Load X and Store X instructions also have accumulator modes although Increment Accumulator and Decrement Accumulator have been reserved for other purposes (NOP and DEX).

It should be noted for documentation purposes that the X instructions have a special mode of addressing in which register Y is used for all indexing operations; thus, instead of Zero Page Indexed by X, X instructions have Zero Page Indexed by Y, and instead of having Absolute Indexed by X, X instructions have Absolute Indexed by Y.

Group Three Instructions

There are two major classifications of Group Three instructions.

Occupying about half of the OPCODE space for the Group Three instructions are Compare X (CPX) and the instructions that modify the Y index register: Load Y (LDY), Store Y (STY), Compare Y (CPY).

Increment X (INX) and Increment Y (INY) are special subsets of the Compare X (CPX) and Compare Y (CPY) instructions.

All of the branch instructions—BCC, BCS, BEQ, BMI, BNE, BPL, BVC, and BVS— are in Group Three and use only the Relative addressing mode.

All of the flag operations—CLC, SEC, CLD, SED, CLI, SEI, and CLV— are in Group Three and use only use only the Implied addressing mode.

All of the push and pull instructions—PHA, PHP, PLA, and PLP— and [other] stack operation instructions—BRK, JSR, RTI, and RTS— are Group Three instructions. (Note that I add RTI and RTS to the “stack” subgroup.)

The JMP and BIT instructions are also included in this group.

There is no common addressing mode available to members of this group. Load Y, Store Y, BIT, Compare X and Compare Y have Zero Page and Absolute. All of the Y and X instructions allow Zero Page Indexed operations and Immediate.

Instruction List, Alphabetic by Mnemonic Definition of Instruction Groups

MCS6501-MCS6505 Microprocessor Instruction Set – Alphabetic Sequence

Addressing Modes

Each instruction uses one or more addressing mode(s).

The addressing modes used by the 6502 include those in the table below. Note that the number of bytes required for each instruction depends on the addressing mode and includes one byte for the opcode and one byte or two bytes for operands, depending on the addressing mode.

The table below includes the full name of each operating mode. Words and terms often ommitted appear in brackets.

The colors in the table are used to identify and highlight addressing modes of opcodes in tables that follow.

Note that a “pointer” is a memory address that contains another memory address that identifies the location of a value. (An intermediate location is used to locate a value indirectly; this method of locating values is called indirection.)

Opcodes

Microprocessors use a unique number to represent each combination of instruction and addressing mode available for its use. Each of these numbers is called an operation code, which is frequently abbreviated as “opcodes”. (In short: instruction + addressing mode = opcode .)

Like other microprocessors (especially of such early and economical design), the 6502 uses single 8-bit bytes to encode both the function of each operation to be performed and which addressing mode(s) to use with it.

Microprocessors such as the 6502 store their opcodes as single 8-bit bytes, so they can have can have up to 256 (2⁸) opcodes.

For its 56 instructions and their variants, the 6502 uses only 151 of the 256 possible opcodes.

(In contrast, the more-expensive Motorola 6800—a precessor to the 6502 that shared many of its designers—included 197 opcodes to represent its 72 instructions and the various addressing modes that it may use.)

Please note that the opcodes described herein apply to the 6500 family including 6502 and 6502B, but not next-generation variants from the Western Design Center (WDC) such as the CMOS 65C02.

Opcode Maps

The instructions and their variations have often been presented in tables often called “opcode maps”. These generally present terse information about each opcode (a mnemonic abbreviation and sometimes more) often in square tables of 16 columns by 16 rows, arranged in numerical order based on each opcode number’s lowest 4 bits (corresponding to the least-significant of its two hexadecimal digits) along one axis and the highest 4 bits (the most-significant digit, or MSD) along the other.

(Groups of consecutive 4 bits are sometimes referred to as a digit, nibble, or nybble—the last two apparently differentiated by whether one sees such a digit as a collection of four “bits” or half of a “byte”, respectively.)

Notes:
*: ROR was not included until after June 1976.

In the table above, dark gray areas indicate operation codes that are undefined for the 6502.

In the table above and those that follow, opcodes that use addressing modes that deviate from the pattern are denoted with thick black borders.

The Other Values

Of the 256 possible values that could be presented to the 6502 as an opcode, its designers defined only 151 values as valid opcodes.

I refer to the remaining 105 herein simply as “extra opcodes”, though some describe them using terms such as “illegal opcodes”, “invalid instructions”, “undefined”, “undocumented instructions”, “unimplemented operations”, “unintended opcodes”, or “unofficial”. (To differentiate the mneumonic abbreviations of extra opcodes, I enclose them in brackets.)

For these extra opcodes, I rely on data (and reproduce text directly) from Extra Instructions Of The 65XX Series CPU by Adam Vardy, who cites Joel Shepherd (“Extra Instructions”, COMPUTE!, October 1983), Raymond Quirling (“6510 Opcode” The Transactor, March 1986), Jim Butterfield (“Strange Opcodes”, COMPUTE!, March 1993), and John West with Marko M„kel„ (“64doc” file, 1994/06/03).

Extra Instructions, Alphabetic by Mnemonic Definition of Instruction Groups

See also the alphabetic list of non-extra opcodes.

The following summary of 22 extra instructions (plus apparent extensions of two non-extra instructions) uses the same notation used for other opcodes.

Note that 18 of the 22 extra instructions use opcodes in the fourth group of opcodes (outside the three groups containing non-extra opcodes); the other instructions are marked with an asterisk (*).

^* Not in Group 4

Hazards of the Extra Opcodes

If a 6502 seeking an opcode for its next instruction should instead encounter one of theese extra values, its behavior could be unpredictable and possibly undesirable, such as halting operation until it is turned off and on again.

This problem is compounded by the many variants within the 6500 family and potential variations in their implementations and processes used by their many different manufacturers, which could also change over time. (Notably, 6500 family devices did not include the ROR instruction until after June 1976.)

Still, some intrepid programmers could find utility in using them (hopefully only under very well-controlled conditions), and examining these extra opcodes could provide a glimpse of insight into the 6502’s inner workings and/or a roadmap for expanding functions of future devices.

Mapping All of the Possible Opcodes

The extra opcodes fill in the opcode map, as in the table below.

Notes:
HLT: Thought addressing modes likely match those in neighboring columns, these opcodes halt program execution making the modes irrelevant.
†: One source identifies marked SKB opcodes (82, C2, E2) as possibly causing some devices to halt (HLT); SXA is described as “possibly unreliable”.
*: ROR was not included until after June 1976.

Opcode Relationships

With the 6502 microprocessor (and likely others), opcode maps such as those above obscure the relationships between many opcodes.

In the 6502, the 8 bits of an opcode (with the most-significant bit first, on the left) can be described as following the pattern AAABBBCC, where BBB represents the addressing mode, CC indicates the instruction group (except CC = 00 represents “Group 3” rather than a “Group 0”), and the remaining bits AAA specify the instruction to be performed.

So, alternate presentations of the opcode maps seem worthwhile.

Grouping Opcodes by Addressing Mode

Opcodes with the same addressing modes can be grouped together by re-grouping the rows based on the value of bit 5, putting those with an even-numbered most-significant byte (MSB) at the top and those using odd numbers at the bottom.

This reveals potential subsets in the upper two quarters, and some grouping among special cases in the fourth quarter.

Notes:
HLT: Thought addressing modes likely match those in neighboring columns, these opcodes halt program execution making the modes irrelevant.
†: One source identifies marked SKB opcodes (82, C2, E2) as possibly causing some devices to halt (HLT); SXA is described as “possibly unreliable”.
*: ROR was not included until after June 1976.

Opcodes by Group and Addressing Mode

The 6502 opcodes seem even easier to understand when the bits in the opcode are re-ordered from AAABBBCC into rows by group and instruction as CCAAA and in columns by addressing mode BBB.

(For simplicity, I keep the bits within those groups in their original order. I also don’t invert any bits; doing so is sometimes useful to aid understanding, but not in this case.)

Applying this transformation to the above opcode map tables, the top half of every fourth column (starting from x0) form the left half of Group 3, and the bottom half of every fourth column form the left half of Group 3, as they appear at the top of the the table below.

Similarly, following this pattern for opcodes from columns x1, x2, and x3 form Group 1, Group 2, and a new group containing only extra opcodes, which could be treated as a new Group 4.

For example, the instruction for No Operation (NOP) is represented numerically as hexadecimal 0xEA or binary 1110 1010. Divided into groups using the pattern AAABBBCC, this is 111 010 10. Swapping the order of groups AAA and CC yields binary 10 111 (decimal 23) with the address mode remaining in group BBB as 010 (decimal 2), which in the following table correlate to the headings for rows and columns, respectively.

The following table uses the same color codings (for addressing modes and instruction types) and the thick black borders (indicating instructions that deviate somewhat from the pattern) as in the previous opcode map tables.

Notes:
*: ROR was not included until after June 1976
for each of these conditions that apply:
B: If the conditional branch is taken, add one cycle to the minimum number of cycles shown in a given range.
P: If crossing a page boundary, add one cycle (two if branching) to the minimum number of cycles shown in a given range.

Opcode Totals

The table below summarizes opcode groups and some color codes used for backgrounds used for some opcodes in the table above. (Their addressing modes are coded based on colors in a previous table.)

What Opcode Relationships Reveal

Some opcodes reveal shadowing, which is an artifact of course decoding (the use of only enough logic to locate something at a desired location within a certain numerical space, but not enough to filter out its appearence at other locations). Some opcodes enable inferences about internal structures such as connections of data buses, etc.

Instructions – Alphabetic by Mnemonic with Opcodes, Execution Cycles and Memory Requirements

See also the alphabetic list of extra opcodes.

The following notation applies to this summary:

A

Accumulator

X, Y

Index Registers

M

Memory

P

Processor Status Register

S

Stack Pointer

✓

Change

–

No Change

+

Add

∧

Logical AND

−

Subtract

⩝

Logical Exclusive OR

↑

Transfer from Stack

↓

Transfer to Stack

→

Transfer to

←

Transfer to

∨

Logical OR

PC

Program Counter (including High Byte and Low Byte)

PCH

Program Counter High Byte

PCL

Program Counter Low Byte

Oper

Operand

#

Immediate Addressing Mode

Note: Following each table (except for NOP) is a copy of the Section in the MCS6500 Microcomputer Family Programming Manual (1975 First Edition) in which the instruction is defined and discussed.

Operation: A + M + C → A, C

This instruction adds the value of memory and carry from the previous operation to the value of the accumulator and stores the result in the accumulator.

The symbolic representation for this instruction is A + M + C → A.

It is a “Group One” instruction and has the following addressing modes: Immediate; Absolute; Zero Page; Absolute,X; Absolute,Y; Zero Page,X; Indexed Indirect; and Indirect Indexed.

State Dependencies and Changes

D

→ not affected; state affects operation

A

→ affects operation

A

← A + M + C

C

← set (1) if the sum of a binary add exceeds 255 or when the sum of a decimal add exceeds 99; otherwise cleared (0)

V

← set (1) if the sign or bit 7 is changed due to the result exceeding +127 or −128; otherwise cleared (0)

N

← set (1) if the accumulator result contains bit 7 on; otherwise cleared (0)

Z

← set (1) if the accumulator result is 0; otherwise cleared (0)

ADC does not affect X, Y, S, PC, nor bits { B, D, I }.

Exposition

The ninth bit of the result is stored in the carry flag and the remaining 8 bits reside in the accumulator. The carry flag can be thought of as a flag bit which is remote from the accumulator itself but which is directly affected by accumulator operations as though it were a ninth bit in the accumulator. The primary reason for not viewing the carry bit as merely a ninth bit in the accumulator is that one has program control over its state by being able to set (to “1”) or clear (to “0”) the bit and, of course, it is not part of the 8-bit accumulator in data transfer operations. Examples employing the Add with Carry operation follow.

*(A) and (M) refer to the “contents” of the accumulator and “contents” of memory respectively.

While the accumulator contains “5,” the carry flag signals the user that the result exceeded 255 and, therefore, the result can be properly interpreted as 256 + 5 = 261.

Operation: A ∧ M → A

Logical AND to the accumulator

The AND instructions transfer the accumulator and memory to the adder which performs a bit-by-bit AND operation and stores the result back in the accumulator.

This is symbolically represented by A ∧ M → A.

AND is a “Group One” instruction having addressing modes of Immediate; Absolute; Zero Page; Absolute,X; Absolute,Y; Zero Page,X; Indexed Indirect; and Indirect Indexed.

State Dependencies and Changes

A

→ affects operation

A

← A ∧ M

Z

← set (1) if the result in the accumulator is 0; otherwise cleared (0)

N

← set (1) if the result in the accumulator has bit 7 on; otherwise cleared (0)

AND does not affect X, Y, S, PC, nor bits { V, B, D, I, C }.

Applications

One of the uses for the AND operation is that of clearing a bit in memory. In the example below, a byte is loaded into the accumulator and the AND instruction clears the accumulator bit 3 to 0. The accumulator is then stored back into memory, thereby clearing the bit.

Operation: C ← 76543210 ← 0

The shift left instruction shifts either the accumulator or the address memory location 1 bit to the left, with the bit 0 always being set to 0 and the bit 7 output always being contained in the carry flag. ASL either shifts the accumulator left 1 bit or is a read/modify/write instruction that affects only memory.

ASL is a read/modify/write instruction and has the following address ing modes: Accumulator; Zero Page; Zero Page,X; Absolute; Absolute,X

State Dependencies and Changes

A

→ if in Accumulator addressing mode, affects operation

A

← if in Accumulator addressing mode, input A shifted left one bit, with bit 0 cleared (0)

C

← Stores the input bit 7

N

← Made equal to the result bit 7 (bit 6 in the input)

Z

← Set (1) if the result is equal to 0; otherwise cleared (0)

ASL does not affect X, Y, S, PC, nor bits { V, B, D, I }.

Operation: Branch on C = 0

This instruction tests the state of the carry bit and takes a conditional branch if the carry bit is clear (0).

The addressing mode is Relative.

State Dependencies and Changes

BCC affects no flags or registers other than the program counter and then only if the C flag is not on.

C

→ Condition of operation (does not change)

PCL

← If C is clear (0), PCL + signed Oper (adding a cycle); otherwise not changed

PCH

← If C is clear (0) and above yields carry (or borrow), PCH + carry (or borrow) from above (adding another cycle); otherwise not changed

BCC does not affect A, X, Y, S, nor bits { N, V, B, D, I, Z, C }.

Operation: Branch on C = 1

This instruction takes the conditional branch if the carry flag (C) is set (1).

The addressing mode is Relative.

State Dependencies and Changes

BCS does not affect any of the flags or registers except for the program counter and only then if the carry flag is on.

C

→ Condition of operation (does not change)

PCL

← If C is set (1), PCL + signed Oper (adding a cycle); otherwise not changed

PCH

← If C is set (1) and above yields carry (or borrow), PCH + carry (or borrow) from above (adding another cycle); otherwise not changed

BCS does not affect A, X, Y, S, nor bits { N, V, B, D, I, Z, C }.

Operation: Branch on Z = 1

BEQ is the complementary branch to Branch on Result Not Equal (BNE).

BEQ could also be called “Branch on result zero”. It takes a conditional branch whenever the Z flag is on or the previous result is equal to 0.

The addressing mode is Relative.

State Dependencies and Changes

BEQ does not affect any of the flags or registers other than the program counter and only then when the Z flag is set.

Z

→ Condition of operation (does not change)

PCL

← If Z is set (1), PCL + signed Oper (adding a cycle); otherwise not changed

PCH

← If Z is set (1) and above yields carry (or borrow), PCH + carry (or borrow) from above (adding another cycle); otherwise not changed

BEQ does not affect A, X, Y, S, nor bits { N, V, B, D, I, Z, C }.

Operation: A ∧ M, M₇ → N, M₆ → V

Bit 6 and bit 7 are transferred to the status register. If the result of A ∧ M is zero then Z = 1; otherwise Z = 0

This instruction performs an AND between a memory location and the accumulator but does not store the result of the AND into the accumulator.

The symbolic notation is A ∧ M.

The addressing modes are Zero Page and Absolute.

State Dependencies and Changes

A

→

N

← Made equal to bit 7 of the memory being tested

V

← Made equal to bit 6 of the memory being tested

Z

← Made equal to the result of the AND operation between the accumulator and the memory if the result is 0; otherwise clear (0) .

BIT does not affect A, X, Y, S, PC, nor bits { B, D, I, Z }.

Exposition

The BIT instruction actually combines two instructions from the PDP-11 and MC6800, that of TST (Test Memory) and (BIT Test).

This, like the compare test, allows the examination of an individual bit without disturbing the value in the accumulator and is illustra ted by the example below:

The value “MASK” loaded into the accumulator in this example is actually a descriptive title since, this byte is 8 bits, only one of which is a 1. Using this byte in the AND operation inherent in the BIT test will effectively mask out all bits in the memory location under test except that bit position corresponding to the 1 residing in the accumulator. In Example 4.8, the MASK byte is AND'ed to the data found in location ADHl, ADLl and if the bit under test is a l, the branch will be taken; if not a l, the second memory location will be tested with the same mask, etc.

In addition to the nondestructive feature of the bit which allows us to isolate an individual bit by use of the branch equal or branch no equal test, two modifications to the PDP-11 version of that instruction have been made in the MCS650X microprocessor. These are to allow a test of bit 7 and bit 6 of the field examined with the BIT test. This feature is particularly useful in serving polled interrupts and particularly in dealing with the MCS6520 (Peripheral Interface Device). This device has an interrupt sense bit in bit 6 and bit 7 of the status words. It is a standard of the MC6800 bus that whenever possible, bit 7 reflects the interrupt status of an I/O device. This means that under normal circumstances, an analysis of the N flag after a load or BIT instruction should indicate the status of the bit 7 on the I/O device being sampled. To facilitate this test using the Bit instruction, bit 7 from the memory being tested is set into the N flag irrespective of the value in the accumulator.

This is different from the bit instruction in the MC6800 which requires that bit 7 also be set on the accumulator to set N. The advantage to the user is that if he they decides to test bit 7 in the memory, it is done directly by sampling the N bit with a Bit followed by branch minus or branch plus instruction. This means that 1/0 sampling can be accomplished at any time during the operation of instructions irrespective of the value preloaded in the accumulator.

Another feature of the BIT test is the setting of bit 6 into the V flag. As indicated previously, the V flag is normally reserved for overflow into the sign position during an add and subtract instruction. In other words, the V flag is not disturbed by normal instructions. When the BIT instruction is used, it is assumed that the user is trying to examine the memory that he is they are testing with the BIT instruction. In order to receive maximum value from a BIT instruction, bit 6 from the memory being tested is set into the V flag.

In the case of a normal memory operation, this just means that the user should organize his their memory such that both of his their flags to be tested are in either bit 6 or bit 7, in which case an appropriate mask does not have to be loaded into the accumulator prior to implementing the BIT instruction. In the case of the MCS6520, the BIT instruction can be used for sampling interrupt, irrespective of the mask. This allows the programmer to totally interrogate both bit 6 and bit 7 of the MCS6520 without disturbing the accumulator. In the case of the concurrent interrupts, i.e., bit 6 and bit 7 both on, the fact that the V flag is automatically set by the BIT instruction allows the user to postpone testing for the “6th bit on” until after he has they have totally handled the interrupt “for bit 7 on” unless he they performs an arithmetic operation subsequent to the BIT operation.

Operation: Branch on N = 1

BMI is the complementary branch to Branch on Result Plus (BPL).

BMI takes the conditional branch if the N bit is set.

The mode of addressing for BMI is Relative.

State Dependencies and Changes

BMI does not affect any of the flags or any other part of the machine other than the program counter and then only if the N bit is on.

N

→ Condition of operation (does not change)

PCL

← If N is set (1), PCL + signed Oper (adding a cycle); otherwise not changed

PCH

← If N is set (1) and above yields carry (or borrow), PCH + carry (or borrow) from above (adding another cycle); otherwise not changed

BMI does not affect A, X, Y, S, nor bits { N, V, B, D, I, Z, C }.

Operation: Branch on Z = 1

BNE is the complementary branch to Branch on Result Equal (BEQ).

BNE could also be called “Branch on result not zero”. It tests the Z flag and takes the conditional branch if the Z flag is not on, indicating that the previous result was not zero.

The addressing mode is Relative.

State Dependencies and Changes

Z

→ Condition of operation (does not change)

PCL

← If Z is clear (0), PCL + signed Oper (adding a cycle); otherwise not changed

PCH

← If Z is clear (0) and above yields carry (or borrow), PCH + carry (or borrow) from above (adding another cycle); otherwise not changed

BNE does not affect A, X, Y, S, nor bits { N, V, B, D, I, Z, C }.

Operation: Branch on N = 0

BPL is the complementary branch to Branch on Result Minus (BMI).

BPL is a conditional branch which takes the branch when the N bit is clear (0). BPL is used to test if the previous result bit 7 was off (0) and Branch on Result Minus is used to determine if the previous result was minus or bit 7 was on (1).

The addressing mode is Relative.

State Dependencies and Changes

The instruction affects no flags or other registers other than the P counter and only affects the P counter when the N bit is clear (0).

N

→ Condition of operation (does not change)

PCL

← If N is clear (0), PCL + signed Oper (adding a cycle); otherwise not changed

PCH

← If N is clear (0) and above yields carry (or borrow), PCH + carry (or borrow) from above (adding another cycle); otherwise not changed

BPL does not affect A, X, Y, S, nor bits { N, V, B, D, I, Z, C }.

Operation: Forced Interrupt PC + 2 ↓ P ↓

The Break command causes the microprocessor to go through an interrupt sequence under program control. This means that the program counter of the second byte after the BRK is automatically stored on the stack along with the processor status at the beginning of the break instruction.

The microprocessor then transfers control to the interrupt vector.

Note: A BRK command cannot be masked by setting I.

Symbolic notation for BRK is PC + 2↓, (FFFE)→PCL, (FFFF)→PCH.

The BRK is a single byte instruction and its addressing mode is Implied.

State Dependencies and Changes

Other than changing the program counter, the break instruction changes no values in either the registers or the flags.

PCL

← (FFFE)

PCH

← (FFFF)

S

← PC + 2

B

← 1

BRK does not affect A, X, Y, nor bits { N, V, D, I, Z, C }.

Exposition

As is indicated, the most typical use for the break instruction is during program debugging. When the user decides that the particular program is not operating correctly, he they may decide to patch in the break instruction over some code that already exists and halt the program when it gets to that point. In order to minimize the hardware cost of the break which is applicable only for debugging, the microprocessor makes use of the interrupt vector point to allow the user to trap out that a break has occurred. In order to know whether the vector was fetched in response to an interrupt or in response to a BRK instruction, the B flag is stored on the stack, at stack pointer plus 1, containing a one in the break bit position, indicating the interrupt was caused by a BRK instruction. The B bit in the stack contains 0 if it was caused by a normal IRQ. Therefore, the coding to analyze for this is as follows in Example 9.7.

This coding can be inserted any place in the interrupt processing routine. During debugging, if the user can afford the execution time, it should be placed immediately after the save routine. If not, it can be put at the end of the polling routine which gives a priority to the polling devices as far as servicing the interrupts. However, it should be noted that in order not to lose the break, the returns from all interrupts during debugging should go through an equivalent routine.

Once the user has determined that the break is on, a second analysis and correction must be made. It does not operate in a normal manner of holding the program counter pointing at the next location in memory during the BRK instruction. Because of this, the value on the stack for the program counter is at the break instruction plus two. If the break had been patched over an instruction, this is usually of no significant consequence to the user. However, if it is desired to process the next byte after the break instruction, the use of decrement memory instructions in the stack must be used.

It is recommended that the user normally takes care of patching programs with break by processing a full instruction prior to returning and then use jump returns.

An interesting characteristic about the break instruction is that its OPCODE is all zero’s (0), therefore, BRK coding can be used to patch fusable link PROMS through a break to an E-ROM routine which inserts patch coding.

An example of using the break to patch with is shown below:

The interrupt vector routine points to:

This coding substitutes:

by use of the BRK and a break processing routine.